This present invention relates to data transfer circuit and method, and particularly to a circuit and a method for transferring data stored in a memory to a communication path such as a communication bus.
FIG. 11 shows configuration of a communication system to which a typical data transfer circuit 1x is applied. This data transfer circuit 1x is connected to a memory 3 through a system bus 2, and transfers data read from the memory 3 to a communication bus 4. Note that although not shown in FIG. 11, a processor which stores the data in the memory 3, various types of peripheral circuits, and the like are connected to the system bus 2.
The memory 3 stores data D_A (hereinafter, referred to as “data for periodic transfer”) which is generated by the processor, the various types of peripheral circuits and the like in synchronization with a cycle for transferring data to the communication bus 4, and data D_B (hereinafter, referred to as “data for non-periodic transfer”) which is generated by them out of synchronization with the cycle for transferring data. The data D_A for periodic transfer is the one such as music data which is periodically generated, and thus required for being transferred in real time. On the other hand, the data D_B for non-periodic transfer is the one such as file data which has been prepared in advance of its transfer, and thus not always required for being transferred in real time.
Further, the memory 3 stores pointer information P_A (hereinafter, referred to as “pointer information for periodic transfer”) which is used for reading the data D_A for periodic transfer, and pointer information P_B (hereinafter, referred to as “pointer information for non-periodic transfer”) which is used for reading the data D_B for non-periodic transfer. As shown in FIG. 12, each of the pointer information P_A and P_B includes a storage destination address 201 of the data on the memory 3, a data length 202, a transfer type 203 which indicates whether or not the data should be transferred in synchronization with the cycle for transferring data, and a data ID (Identifier) 204. The transfer type 203 is set to “periodic transfer” in a case of the data D_A (pointer information P_A) for periodic transfer, and set to “non-periodic transfer” in a case of the data D_B (pointer information P_B) for non-periodic transfer. Note that although not shown in FIG. 12, each of the pointer information P_A and P_B includes an indicator which indicates whether or not the data is the final one among continuous data, an indicator which indicates the validity/invalidity of the pointer information itself, and the like, in addition to the above-mentioned address 201, data length 202, transfer type 203, and data ID 204.
In operation, as shown in FIG. 13, the data transfer circuit 1x waits for the start of a frame (Step T1). The frame means a time interval between cycles for transferring data (i.e., a transfer time unit of the communication bus 4). The start of the frame means the coming of a certain cycle for transferring data.
When the frame is started, the data transfer circuit 1x schedules the order of transferring the data (Step T2). At this time, the data transfer circuit 1x allocates a period immediately after the start of the frame for the periodic transfer, and allocates the remaining period for the non-periodic transfer. Specifically, the data transfer circuit 1x firstly determines a data ID of data D_A for periodic transfer to be the subject of the periodic transfer, and then determines a data ID of data D_B for non-periodic transfer to be the subject of the non-periodic transfer. In a case where plural pieces of data D_A for periodic transfer are stored in the memory 3, the data transfer circuit 1x selects one piece of the data D_A for periodic transfer in ascending order of the data ID 204 (ID value), for example. Similarly, in a case where plural pieces of data D_B for non-periodic transfer are stored in the memory 3, the data transfer circuit 1x selects one piece of the data D_B for non-periodic transfer in ascending order of the data ID 204.
Then, until completion of transfer with respect to all data IDs scheduled at the above-mentioned Step T2 (Step T3), the data transfer circuit 1x repeatedly executes processes shown at the following Steps T4 to T7.
Assume that upon transfer in a frame F1 shown in FIG. 14, the data transfer circuit 1x selects a data ID=“A1” of data D_A1 for periodic transfer, and a data ID=“B1” of data D_B1 for non-periodic transfer.
In this case, as shown in FIG. 14, the data transfer circuit 1x reads pointer information P_A1 for periodic transfer, which includes the data ID=“A1”, from the memory 3 through the system bus 2 (Step T4). The data transfer circuit 1x stores the read pointer information P_A1 in an internal storage area (Step T5).
Then, the data transfer circuit 1x analyzes the pointer information P_A1 (Step T6). Specifically, the data transfer circuit 1x refers to the data length 202 indicated in the pointer information P_A1, and thus determines a data length (hereinafter, referred to as “data transfer length”) which can be transferred during a period allocated for transferring the data D_A1 for periodic transfer. In this example, assume that there is allocated a period during which the entire data D_A can be transferred, and the data length 202 is determined as the data transfer length.
Then, the data transfer circuit 1x executes a process to transfer the data D_A1, based on the pointer information P_A1 and the data transfer length determined at the above-mentioned Step T6 (Step T7).
Specifically, the data transfer circuit 1x firstly reads data corresponding to the data transfer length from the address 201 indicated in the pointer information P_A1. Thus, as shown in FIG. 14, the data D_A1 for periodic transfer is transferred to the data transfer circuit 1x through the system bus 2.
Next, as shown in FIG. 14, the data transfer circuit 1x transfers the read data D_A1 for periodic transfer to the communication bus 4. In more detail, the data transfer circuit 1x divides the data D_A1 into packet length units which are suitable to a communication standard applied to the communication bus 4 (USB (Universal Serial Bus) standard, PCI (Peripheral Component Interconnect) Express standard, or the like). Then, the data transfer circuit 1x appends a packet number (sequence number) to each packet to be transferred to the communication bus 4. When an acknowledgment (handshake packet) is received from a transfer destination device, the data transfer circuit 1x determines that it has succeeded in transferring the data D_A1. On the other hand, when a negative acknowledgement (reception failure, retransmission request, halt request, or the like) is received from the transfer destination device, the data transfer circuit 1x determines that it has failed in transferring the data D_A1, and then executes a process to retransmit the packets within the period allocated for transferring the data D_A1. Thus, as shown in FIG. 14, the data D_A1 for periodic transfer is transferred to the communication bus 4.
Then, the data transfer circuit 1x returns to the above-mentioned Step T4, and thus reads pointer information P_B1 for non-periodic transfer, which includes the data ID=“B1”, from the memory 3 through the system bus 2 as shown in FIG. 14. The data transfer circuit 1x moves to the above-mentioned Step T5, and thus overwrites the internal storage area with the read pointer information P_B1.
Then, the data transfer circuit 1x moves to the above-mentioned Step T6, and thus analyzes the pointer information P_B1. Assume that the entire data D_B1 for non-periodic transfer cannot be transferred within a period allocated for transferring the data D_B1. In this case, the data transfer circuit 1x determines, as the data transfer length, a data length which is equivalent to a part of the data D_B1.
Then, the data transfer circuit 1x moves to the above-mentioned Step T7, and thus executes a process to transfer the data D_B1, based on the pointer information P_B1 and the determined data transfer length.
Thus, as shown in FIG. 14, the part of the data D_B1 for non-periodic transfer is transferred to the data transfer circuit 1x through the system bus 2, and then transferred to the communication bus 4.
Note that although not shown in FIGS. 13 and 14, the data transfer circuit 1x overwrites the address 201 indicated in the pointer information P_B1 on the memory 3 with an address corresponding to the remaining data of the data D_B1. Further, the data transfer circuit 1x overwrites the data length 202 indicated in the pointer information P_B1 on the memory 3 with a data length of the remaining data of the data D_B1. In other words, the pointer information P_B1 is transferred in the system bus 2 from the data transfer circuit 1x to the memory 3.
Further, at the above-mentioned Step T3, the data transfer circuit 1x determines that the transfer with respect to all data IDs scheduled at the above-mentioned Step T2 has been completed, thereby terminating the transfer in the frame F1.
After that, when a frame F2 is started as shown in FIG. 14, the data transfer circuit 1x newly selects a data ID=“A2” of data D_A2 for periodic transfer, and continues to select the data ID=“B1” of the data D_B1 for non-periodic transfer at the above-mentioned Step T2. Then, the data transfer circuit 1x executes the processes shown at the above-mentioned Steps T4 to T7, with respect to each of the data IDs=“A2” and “B1”.
Firstly, as shown in FIG. 14, the data transfer circuit 1x reads pointer information P_A2 for periodic transfer, which includes the data ID=“A2”, from the memory 3 through the system bus 2. The data transfer circuit 1x overwrites the internal storage area with the read pointer information P_A2.
Then, the data transfer circuit 1x analyzes the pointer information P_A2, thereby determining, as the data transfer length, the data length 202 indicated in the pointer information P_A2. The data transfer circuit 1x reads data corresponding to the data transfer length from the address 201 indicated in the pointer information P_A2. Thus, as shown in FIG. 14, the data D_A2 for periodic transfer is transferred to the data transfer circuit 1x through the system bus 2.
Then, as shown in FIG. 14, the data transfer circuit 1x transfers the read data D_A2 for periodic transfer to the communication bus 4.
Then, as shown in FIG. 14, the data transfer circuit 1x reads pointer information P_B1 for non-periodic transfer, which includes the data ID=“B1”, from the memory 3 through the system bus 2. The data transfer circuit 1x overwrites the internal storage area with the read pointer information P_B1.
Then, the data transfer circuit 1x analyzes the pointer information P_B1. Assume that the entire remaining data of the data D_B1 for non-periodic transfer can be transferred within a period allocated for transferring the data D_B1. In this case, the data transfer circuit 1x determines, as the data transfer length, the remaining data length of the data D_B1 for non-periodic transfer (i.e., the data length 202 indicated in the pointer information P_B1). The data transfer circuit 1x reads data corresponding to the data transfer length from the address 201 indicated in the pointer information P_B1. Thus, as shown in FIG. 14, the remaining data of the data D_B1 for non-periodic transfer is transferred to the data transfer circuit 1x through the system bus 2.
Then, as shown in FIG. 14, the data transfer circuit 1x transfers the read remaining data of the data D_B1 for non-periodic transfer to the communication bus 4.